1. Field of the Invention
The invention relates to a semiconductor device having a double RESURF structure and a method for manufacturing a semiconductor device.
2. Related Art
A high voltage isolation structure having a double RESURF structure has been known as a method for achieving a high breakdown voltage in a semiconductor device with a high breakdown voltage. FIG. 13 is a conceptual cross-sectional view illustrating a semiconductor device including the high voltage isolation structure having the double RESURF structure. As shown in FIG. 13, the double RESURF structure means a structure in which an n-type semiconductor layer 102 is interposed between p-type semiconductor layers 101 and 103.
In the semiconductor device having the double RESURF structure, in order to ensure a high breakdown voltage, the total amount of charge Qp per unit area in the p-type diffusion layer 103 and the total amount of charge Qn per unit area in the n-type diffusion layer 102 need to be adjusted such that the following Expressions (1) to (3), which are double RESURF conditions, are satisfied, as described in “Design and Optimization of Double-RESURF High-Voltage Lateral Devices for a Manufacturable Process,” IEEE Trans. on Electron Devices, (U.S.), IEEE, JULY 2003, VOL. 50, NO. 7, PP. 1697-1701, also referred to herein as “Non-patent Document 1.” The following Expression (1) corresponds to Expression (9) in the following Non-patent Document 1. The following Expression (2) corresponds to Expression (10) in the following Non-patent Document 1. The following Expression (3) corresponds to Expressions (11) and (12) in the following Non-patent Document 1.
The total amount of charge per unit area in each diffusion layer is equivalent to the total net amount of impurities per unit area in each diffusion layer. The total net amount of impurities per unit area in the diffusion layer is the difference between the total amount of p-type impurities per unit area in the diffusion layer and the total amount of n-type impurities per unit area in the diffusion layer, which is obtained by integrating the amount of p-type impurities per unit volume and the amount of n-type impurities per unit volume with respect to the depth of the diffusion layer in an impurity profile of the diffusion layer in the depth direction.
[Equation 1]Qp≦1.4×1012[/cm2]  (1)
[Equation 2]Qn≦2.8×1012[/cm2]  (2)
[Equation 3]Qn−Qp≦1.4×1012[/cm2]  (3)
As can be seen from Expressions (1) to (3), the balance between the total amount of charge Qp per unit area in the p-type diffusion layer 103 and the total amount of charge Qn per unit area in the n-type diffusion layer 102 needs be optimally maintained in the ranges represented by Expressions (1) to (3) in order to ensure a high breakdown voltage in the double RESURF structure. Here, in the total amount of charge or the total amount of impurities, the term “total” is used in order to indicate the total amount which is integrated in the depth direction of each layer.
FIGS. 16A-16D are explanatory diagrams illustrating terms. FIG. 16A is a diagram illustrating an ion implantation dose. The ion implantation dose means the amount of impurities before impurity ions which are implanted into the silicon layer enter the silicon layer. Hereinafter, the dose of ions implanted in order to form the diffusion layer is referred to as the dose of the diffusion layer. FIG. 16B is a diagram illustrating the total amount of impurities per unit area in a straight portion 15 of a high voltage isolation structure 14, which will be described below. FIG. 16C is a diagram illustrating the total amount of impurities per unit area in a corner portion 16 of the high voltage isolation structure 14, which will be described below. FIG. 16D is a diagram illustrating the total net amount of impurities per unit area in the high voltage isolation structure 14. The total amount of charge per unit area is the product of the net amount of impurities per unit area and an elementary charge q (=1.602×10−19 coulombs). The total amount of impurities is the amount of impurities after the impurity ions which are implanted into the silicon layer enter the silicon layer. Therefore, as shown in FIG. 16B, when the silicon layer is not covered by the mask, the total amount of impurities is equal to the dose (the total amount of impurities=the dose). On the other hand, as shown in FIG. 16C, when the silicon layer is partially covered by the mask, a small amount of impurity ions is implanted into the silicon layer and the total amount of impurities is less than the dose (the total amount of impurities portion<the dose).
FIGS. 14A and 14B are diagrams illustrating the structure of a semiconductor device 500 including a high voltage isolation structure 64 having a double RESURF structure according to the related art. FIG. 14A is a plan view illustrating a main portion of the semiconductor device 500 and FIG. 14B is a cross-sectional view illustrating the main portion taken along the line A-A and the line B-B of FIG. 14A. The cross-sections taken along the line A-A and the line B-B of FIG. 14A are the same. The high voltage isolation structure 64 is a breakdown voltage structure which separates a low potential region 63 and a high potential region 62 in, for example, an integrated circuit.
In FIG. 14A, the high voltage isolation structure 64 is an annular strip with a constant width which has a substantially rectangular shape in a plan view. The high voltage isolation structure 64 surrounds the high potential region 62. The high voltage isolation structure 64 includes a straight portion 65 and a corner portion 66 which is connected to the end of the straight portion 65 and has a curved shape with a constant curvature.
In FIG. 14B, an n-type diffusion layer 52 with a depth of about 10 μm is formed in a surface layer of a front surface of a p-type silicon substrate 51. A p-type diffusion layer 53 with a depth of about 2 μm is formed in a surface layer of the diffusion layer 52 close to the front surface of the substrate front. The diffusion layer 53 and the silicon substrate 51 are connected to each other through a deep p-type diffusion layer 54, which passes through the n-type diffusion layer 52 in the depth direction, in an outer circumferential portion of the substrate. The high potential region 62, which is the n-type diffusion layer 52, is formed inside the n-type diffusion layer 52 surrounded by the high voltage isolation structure 64. The configuration of the high voltage isolation structure 64 in the vertical direction (depth direction) is a three-layer double RESURF structure in which the p-type diffusion layer 53, the n-type diffusion layer 52, and the p-type silicon substrate 51 overlap each other in this order from the front surface of the substrate.
The diffusion layer 52 is electrically connected to an electrode 59 with a high potential through a high-concentration n-type region 56. The diffusion layer 53 is electrically connected to an electrode 60 with a low potential through a high-concentration p-type region 57. The electrode 59 and the electrode 60 extend on an interlayer insulating film 58 and are electrically connected to a field plate 61a and a field plate 61b, respectively. Reference numeral 55 indicates a LOCOS (Local Oxidation of Silicon) film.
Next, the operation of the high voltage isolation structure 64 will be described. When the potential of the electrode 59 increases, with the electrode 60 fixed to a GND potential, the potential of the high potential region 62 increases through the diffusion layer 52. Then, a depletion layer is spread from the pn junction between the diffusion layer 52 and the diffusion layer 53 and the pn junction between the diffusion layer 52 and the silicon substrate 51, and the diffusion layer 52 and the diffusion layer 53 are completely depleted at the potential, hundreds of volts, of the electrode 59. In this way, the concentration of the electric field between the electrode 59 and the electrode 60 is suppressed. Therefore, it is possible to obtain a high breakdown voltage between the electrode 59 and the electrode 60 and to increase the potential of the high potential region 62 to be higher than that of the low potential region 63 on the same substrate.
Japanese Patent Application Publication No. JP 3778061 A (also referred to herein as “Patent Document 1”) discloses a technique in which a high potential region and a breakdown voltage structure region of a p offset region which is shallower than the high potential region are formed using the same mask in order to reduce costs and the bottom of the formed breakdown voltage structure region has a waveform shape.
Japanese Patent Application Publication No. JP 3356586 A (also referred to herein as “Patent Document 2”) discloses a technique in which the layout of an extended drain is improved to increase the breakdown voltage of a turn-back portion which is formed when a horizontal MOSFET semiconductor device is laid out on a chip, thereby increasing the breakdown voltage of the entire horizontal MOSFET semiconductor device.
Japanese Patent Application Publication No. JP 3456054 A (also referred to herein as “Patent Document 3”) discloses an example in which an n+ region that functions as a stopper for a depletion layer is formed in a surface layer of an n drift layer and the bottom of the n+ region only in a corner portion is formed in a waveform shape, thereby improving the breakdown voltage. Japanese Patent Application Publication No. JP 3802935 A (also referred to herein as (“Patent Document 4”) discloses a technique in which, in a double RESURF structure in which a depletion layer is spread, the distance between a main electrode and a pn junction, which are arranged in the double RESURF structure, in a corner portion in which the depletion layer is likely to be spread is more than that in a straight portion, thereby improving the breakdown voltage.
Japanese Patent Application Publication No. JP 4534303 A (also referred to herein as “Patent Document 5”) discloses a technique in which an n layer on the surface of a breakdown voltage structure portion is formed by a p layer and an n layer to improve the breakdown voltage.
However, in the double RESURF structure shown in FIG. 14, the optimum condition (optimum value) of the total net amount of charge per unit area in each diffusion layer 52 or 53 or obtaining a maximum breakdown voltage (which is equivalent to the total net amount of impurities per unit area) is different in the straight portion (hereinafter, simply referred to as a straight portion) 65 and the corner portion (hereinafter, simply referred to as a corner portion) 66 of the high voltage isolation structure 64. It is presumed that this is because the spreading of the depletion layer is different in the straight portion 65 and the corner portion 66.
FIG. 15 is a characteristic diagram illustrating the simulation result of the relationship between the dose of ions implanted into the p-type diffusion layer 53 and the breakdown voltage in the straight portion 65 and the corner portion 66 of the semiconductor device 500 shown in FIG. 14. The dose on the horizontal axis is the total amount of impurity ions implanted per unit area and is obtained by integrating the amount of impurities per unit volume in the depth direction. In addition, the dose of the n-type diffusion layer 52 is 4.0×1012/cm2 and the dose of the p-type diffusion layer 53 is the same in the straight portion 65 and the corner portion 66. That is, the p-type diffusion layers 53 in the straight portion 65 and the corner portion 66 are formed at the same time by ion implantation.
As can be seen from FIG. 15, the peak of a breakdown voltage curve 71 which is calculated by a simulation for the dose in the straight portion 65 deviates from the peak of a breakdown voltage curve 72 which is calculated by a simulation for the dose at the peak of the corner portion 66. Therefore, the optimum value of the dose of the p-type diffusion layer 53 (the dose at which a peak breakdown voltage is obtained in the breakdown voltage curves 71 and 72 for a dose) deviates to a small dose side in the corner portion 66 with respect to the straight portion 65. The peak breakdown voltage in the corner portion 66 is lower than that in the straight portion 65. This is because the electric field intensity of the corner portion 66 is more than the electric field intensity of the straight portion 65.
As described above, the breakdown voltage curves 71 and 72 which are calculated by a simulation for the dose in the straight portion 65 and the corner portion 66 deviate from each other. Therefore, the breakdown voltage of the element is controlled and reduced along the lower one of the two breakdown voltage curves 71 and 72.
In FIG. 15, the peak value of the breakdown voltage of the element is the breakdown voltage of an intersection between the breakdown voltage curves 71 and 72 which are calculated by simulations. When the dose of the diffusion layer 53 moves in a direction in which the dose is less than the dose of the intersection between the breakdown voltage curves 71 and 72, the breakdown voltage of the element is reduced along the breakdown voltage curve 71 of the straight portion 65. On the other hand, when the dose of the diffusion layer 53 moves in a direction in which the dose is more than the dose of the intersection between the breakdown voltage curves 71 and 72, the breakdown voltage of the element is reduced along the breakdown voltage curve 72 of the corner portion 66. That is, when the actual dose of the diffusion layer 53 deviates from the dose (the optimum value of the dose) of the intersection between the breakdown voltage curves 71 and 72 which are calculated by simulations due to a process variation, the breakdown voltage of the element is rapidly reduced. In addition, the peak value of the breakdown voltage of the element is less than the peak values of the breakdown voltage curves 71 and 72. This will be described in detail below.
In FIG. 1, when a variation in the dose of the diffusion layer 53 due to the process variation is, for example, ±10% and the center value (5.3×1012/cm2) of the dose of the diffusion layer 53 is determined such that a reduction in the breakdown voltage of the element is the minimum, the maximum value of the breakdown voltage of the element is controlled by the breakdown voltage of the corner portion 66 and is 1700 V. The minimum value of the breakdown voltage of the element due to the process variation is the same in the straight portion 65 and the corner portion 66 and is 1400 V.
From the above description, in the high voltage isolation structure 64 with the double RESURF structure, measures capable of further increasing the peak value of the breakdown voltage of the element and further suppressing a reduction in the breakdown voltage of the element due to a process variation are needed.
Patent Document 1 to Patent Document 5 do not disclose a semiconductor device in which, in the high voltage isolation structure with the double RESURF structure, a corner portion is partially covered by a mask such that the amount of impurities implanted into silicon in the corner portion is less than the amount of impurities in a straight portion, thereby improving the breakdown voltage of the element.